1. Field of the Invention
The present invention relates to a method and an apparatus for driving a liquid crystal display, and more particularly, to a method and an apparatus for driving a liquid crystal display that reduces the number of data drive integrated circuits by supplying data to data lines on a time-division basis.
2. Description of the Related Art
In general, a liquid crystal display displays pictures by adjusting the light-transmittance of a liquid crystal using an electric field. For this purpose, the liquid crystal display comprises a liquid crystal display panel where liquid crystal cells are arranged in a active matrix form and a drive circuit for driving the liquid crystal cells of the liquid crystal display panel. In fact, the liquid crystal display, as shown in FIG. 1, comprises data drive integrated circuits 4 (ICs) connected to the liquid crystal display panel 2 through a data tape carrier packages 6 (TCPs), and gate drive integrated circuits 8 connected to the liquid crystal display panel 2 through gate TCPs 10. The liquid crystal display panel 2 comprises a thin film transistor formed at each intersection area of gate lines and data lines, and a liquid crystal cell connected to the thin film transistor. The gate lines are usually arranged horizontally while the data lines are arranged vertically. A gate electrode of the thin film transistor is connected to any one of gate lines, and a source electrode is connected to any one of data lines. The thin film transistor supplies a pixel voltage signal from the data line to the liquid crystal cell in response to a scan signal from the gate line. The liquid crystal cell comprises a pixel electrode connected to a drain electrode of the thin film transistor and a common electrode facing the pixel electrode with liquid crystal material therebetween. The liquid crystal cell adjusts the light transmittance by driving the liquid crystal in response to the pixel voltage signal supplied to the pixel electrode.
Each of the gate drive ICs 8 is mounted on each corresponding gate TCP 10. The gate drive ICs 8 mounted on corresponding gate TCPs 10 are electrically connected to respective gate pads of the liquid crystal display panel 2 through the gate TCPs 10. The gate drive ICs 8 sequentially drive the gate lines of the liquid crystal display panel 2 for each horizontal period (1H). Each of the data drive ICs 4 is mounted on each corresponding data TCP 6. The data drive ICs 4 mounted on respective data TCPs 6 are electrically connected to corresponding data pads of the liquid crystal display panel 2 through the data TCP 6. The data drive IC 4 converts digital pixel data into an analog pixel voltage signal and supplies the pixel voltage signal to the data lines of the liquid crystal display panel 2 for each horizontal period (1H).
To this end, each of the data drive ICs 4, as shown in FIG. 2, comprises a shift register array 12 sequentially supplying a sampling signal, first and second latch arrays 16 and 18 providing a pixel data in response to the sampling signal to output the latched data, a first multiplexor 15 (MUX) array arranged between the first and the second latch arrays 16 and 18, a digital to analog converter (DAC) array 20 converting the pixel data from the second latch array 18 into the pixel voltage signal, a buffer array 26 buffering the pixel voltage signal from the DAC array 20 to output the buffered signal, and a second MUX array 30 selecting a proceeding path of the output of the buffer array 26. The data drive IC 4 further comprises a data register 34 relaying pixel data (R, G, B) supplied from a timing controller (not shown), and a gamma voltage part 36 supplying a positive and a negative gamma voltage necessary to the DAC array 20. Each of the data drive ICs 4 having such components has n channels of data output (for example, 384 or 480 channels) to drive n data lines. FIG. 2 illustrates only 6 channels (DL1 to DL6) of n channels of such a data drive IC 4.
The data register 34 relays the pixel data from the timing controller and supplies the relayed data to the first latch array 16. Herein, the timing controller divides the pixel data into even-numbered pixel data (RGBeven) and odd-numbered pixel data (RGBodd) to supply the divided pixel data to the data register 34 through each transmission line with decreased transmission frequency. The data register 34 outputs the even-numbered pixel data (RGBeven) and the odd-numbered pixel data (RGBodd) input to the first latch array 16 through each transmission line. Herein, each of the even-numbered pixel data (RGBeven) and the odd-numbered pixel data (RGBodd) includes red (R), green (G), and blue (B) pixel data. The gamma voltage part 36 subdivides a plurality of gamma reference voltage input from gamma reference voltage generation part (not shown) by gray levels and outputs the gamma reference voltage.
The shift register array 12 generates sequential sampling signals and supplies the generated signals to the first latch array 16. The shift register array 12 includes the shift registers 14 of n/6 numbers. The first stage of the shift register 14 shown in FIG. 2 shifts a source start pulse (SSP) input from the timing controller according to a source sampling clock signal (SSC) and outputs the shifted source start pulse as the sampling signal and, at the same time, provides the shifted source start pulse to the next stage of the shift register 14 as a carry signal (CAR). The source start pulse (SSP), as shown in FIGS. 3A and 3B, is supplied for each horizontal period (1H) and shifted for each source sampling clock signal (SSC) to be output as the sampling signal.
The first latch array 16 samples the pixel data (RGBeven, RGBodd) from the data register 34 by designated units in response to the sampling signal from the shift register array 12 to latch the sampled pixel data. The first latch array 16 comprises the first latches 13 of the n numbers to latch the pixel data (R, G, B) of n numbers and each of the first latch 13 has the size corresponding to the bit number (for example 3 bit or 6 bit) of the pixel data (R, G, B). The first latch array 16 samples the even-numbered pixel data (RGBeven) and the odd-numbered pixel data (RGBodd), i.e., the pixel data of 6 numbers, for each sampling signal, latches the sampled data and then outputs the latched data at the same time.
The first MUX array 15 determines the proceeding path of the pixel data (R, G, B) provided from the first latch array 16 in response to a polarity control signal (POL) from a timing controller. For this purpose, the first MUX array 15 comprises n+1 number of the first MUXs. Each of the first MUXs 17 receives the output of two adjacent first latches 13 to be selectively output accordance with the polarity control signal (POL). Herein, the output of each of the first latches 13 except first and last ones of the first latches 13 is commonly input to two adjacent first MUXs 17. The output of the first and last ones of the first latches 13 is commonly input to the second latch array 18 and the first MUX 17. The first MUX array 15 controls the pixel data (R, G, B) from each of the first latches 13 to proceed intact to the second latch part 18, or to proceed to the second latch part 18 after being shifted to the right by one in accordance with the polarity control signal (POL). As shown in FIGS. 3A and 3B, the polarity of the polarity control signal (POL) is inverted for each horizontal period (1H). As a result, the first MUX array 15 controls the polarity of the pixel data (R, G, B) by having each of the pixel data (R, G, B) from the first latch array 16 to output to a positive DAC (P DAC) 24 or a negative DAC (N DAC) 22 of the DAC array 20 through the second latch array 18 in response to the polarity control signal (POL).
The second latch array 18 simultaneously latches and outputs the pixel data (R, G, B) input from the first latch array 16 through the first MUX array 15 in response to a source output enable signal (SOE) from the timing controller. Particularly, the second latch array 18 comprises the second latches 19 of the n+1 numbers in consideration when the pixel data (R, G, B) from the first latch array 16 is shifted to the right to be input. The source output enable signal (SOE), as shown in FIGS. 3A and 3B, is generated for each horizontal period (1H). The second latch array 18 latches the pixel data (R, G, B) input at the rising edge of the source output enable signal (SOE) at the same time and outputs the latched data at the falling edge at the same time.
The DAC array 20 converts the pixel data (R, G, B) from the second latch array 18 into the pixel voltage signal using the positive and the negative gamma voltage (GH,GL) from the gamma voltage part 36 and outputs them. For this purpose, DAC array 20 comprises PDAC 24 and NDAC 22 of n+1 numbers. The PDAC 24 and NDAC 22 are arranged alternatively and in parallel to be driven by the dot inversion system. The PDAC 24 converts the pixel data (R, G, B) from the second latch array 18 into positive pixel voltage signal using a positive gamma voltage signal GH. The NDAC 22 converts the pixel data (R, G, B) from the second latch array 18 into negative pixel voltage signal using a negative gamma voltage signal.
Each of the n+1 number of buffers 28 included in the buffer array 26 buffers the pixel voltage signal output from each PDAC 24 and NDAC 22 of the DAC array 20 and outputs them. The second MUX array 30 determines the proceeding path of the pixel voltage signal supplied from buffer array 26 in response to the polarity control signal (POL) from the timing controller. For this purpose, the second MUX array 30 comprises the second MUXs 32 of the n numbers. Each of the second MUXs 32 responds to the polarity control signal (POL) to select the output of any one among two adjacent buffers 28, thereby outputting them to corresponding data line (DL). Herein, the output stage of the buffers 28 except the first and last buffers 28 are held in common by and supply the output to two adjacent second MUXs 32. The second MUX array 30 having such a configuration causes the pixel voltage signal from each of the buffers 28 except the last buffer 28 to correspond intact one-to-one with the data line (DL1 to DL6) in response to the polarity control signal (POL). Further the second MUX array 30 causes the pixel voltage signal from each of the buffers 28 except the first buffer 28 to be shifted to the left by one to correspond one-to-one with the data line (DL1 to DL6) in response to the polarity control signal (POL).
With respect to the polarity control signal (POL), identically with what is supplied to the first MUX array 15, as shown in FIGS. 3A and 3B, its polarity is inverted for each horizontal period (1H). Like this, the second MUX array 30 together with the first MUX array 15 determines the polarity of the pixel voltage signal supplied to the data lines (DL1 to DL6) in response to the polarity control signal. The pixel voltage signal supplied to each data line D1 to D6 through the second MUX array 30 has the polarity contrary to adjacent pixel voltage signals. In other words, as shown in FIGS. 3A and 3B, the pixel voltage signal output to the odd-numbered data lines (DLodd) such as DL1, DL3, DL5, and so on, and the pixel voltage signal output to the even-numbered data lines (DLeven) such as DL2, DL4, DL6, and so on have contrary polarity each other. Also, the polarity of the odd-numbered data line (DLodd) and the even-numbered data line (DLeven) is inverted for each horizontal period (1H) when the gate lines (GL1, GL2, GL3, . . . ) are sequentially driven, and in addition, is inverted for each frame.
However, each of the related art data drive ICs 4 should include the DACs and the buffers of n+1 numbers to drive the data lines of n numbers. As a result, the related art data drive ICs 4 have a disadvantage in that their configuration is complicated and their fabrication cost is relatively high.